Processor Caches

Caching is only supported on the NDS9 processor. The Nintendo DS supports two seperate caches (Harvard architecture), the unified cache feature (von Neumann) is not supported. However, they can be enabled and disabled each.

Instruction CacheData Cache
Capacity8 KiB4 KiB
Configuration4-way set associative4-way set associative
Cache Line Size8 Words / 32 Bytes8 Words / 32 Bytes
OperationsReadRead / Write

Here are some variables defined by the ARM Architecture Reference Manual

Instruction CacheData Cache
LINELEN3232
NSETS6432
ASSOCIATIVITY = NWAYS44

Data cache organisation Fig 1. Data cache organisation

Lockdown functionality

Both the instruction cache and the data cache support the lockdown functionality. It can be controlled by the following CP-15 registers

Cn=9,Cm=0,Op2=0, Data Cache Lockdown Register, Cn=9,Cm=0,Op2=1, Instruction Cache Lockdown Register

╭ 3 ╷         2         ╷         1         ╷         0         ╮
┌─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┐
│1│0│9│8│7│6│5│4│3│2│1│0│9│8│7│6│5│4│3│2│1│0│9│8│7│6│5│4│3│2│1│0│
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